This invention pertains to a square root operation device in a data processor.
Generally, the Newton-Raphson method is the basis of many of square root operation devices. The process of finding the square root of a numeric value A by this method is first to obtain 1/.sqroot.A, thereafter the obtained 1/.sqroot.A being multiplied by A to produce .sqroot.A. The Newton-Raphson method obtains 1/.sqroot.A through a converging calculation. In such a converging calculation, it is known that the closer the initial value of a reciprocal comes to a true value, the lower the number of iteration required to be carried out until a convergent condition has been reached is. Japanese Patent Pub. No. 2-25924 discloses a high-speed square root operation device, according to which a result can be reached after about three to four converging calculations.
However, in such a prior art square root operation device by the Newton-Raphson method, the significand part of a floating-point number input operand is supplied to a multiplying circuit and serves therein as a multiplicand and a multiplier. Because of this, a 53.times.53 bit multiplying circuit corresponding to the bit length of the significand part provided with a leading bit is required if the square root of an IEEE standard double-precision floating-point number is to be found. If multiplication instructions and square root operation instructions are not carried out together, no problems will arise, and even though a multiplying circuit for carrying out a multiplication instruction is used for carrying out a square root operation instruction, no difficulties will arise, either. If there is no data interdependence between multiplication and square root operation instructions, to carry out both of the instructions at the same time requires a 53.times.53 bit multiplying circuit used for square root operations, which cause such a problem that hardware materials greatly increase.
The present invention was made to provide a square root operation device which applies, as a bit length of a multiplier, an operand length for fixed-point numbers, or a multiplying circuit smaller than the bit length of a significand part for floating-point numbers.